The spectrum of nonvolatile memories available today includes the mask programmed ROM, the fusible link bipolar PROMs, the one time programmable (OTP) ROMs, the ultra-violet erasable EPROMs (UV-EPROMs), and the electrically erasable PROMs (EEPROMs). Mask programmed ROMs are the earliest and least flexible type: once programmed, the stored information cannot be altered. UV-EPROMs offer more flexibility, information stored can be erased using ultra violet (UV) light and then electrically reprogrammed into a new pattern. With a single transistor per memory cell UV-EPROM memory arrays allow very high packing densities and low cost per bit. However, even though UV-EPROMs offer firmware designers more flexibility than the mask programmed ROMs, PROMs and the OTP ROMs, it is still not flexible enough for their needs. For a stored program to be updated, the UV-EPROM has to be taken out of its board and either replaced with another UV-EPROM having the new program or erased by putting it in special UV ovens for 10-20 minutes and then programmed with the new code using special purpose hardware programmers.
While EEPROM memories achieve greater flexibility by allowing in-circuit electrical erase and reprogramming, their high cost and small densities have limited their use. The high cost of EEPROM memories is not only due to their complex process but is also due to the fact that the EEPROM memory cell size is three to four times the size of a UV-EPROM cell for the same technology. The high cost per bit has limited the use of EEPROM chip mostly to applications where the user is expected to customize the system environment according to his needs or where the system configuration needs frequent updates.
The flash erase EEPROM (FEEPROM) is the latest addition to the nonvolatile ROM family members. FEEPROM is meant to bridge the gap between existing UV-EPROM and EEPROM by offering the type of ROM which is both electrically erasable as EEPROM and has the high density and cost efficiency of UV-EPROM. In addition to being electrically erasable, erasure of FEEPROM arrays take only few seconds as compared to erase times of 10-20 minutes for UV-EPROM arrays. This provides FEEPROMs with in-circuit program and erase capabilities.
Several FEEPROM memory cell structures have been described in, for example, S. Mukherjee, et al., "A Single Transistor EEPROM Cell And Its Implementation In A 512K CMOS EEPROM," IEDM, paper 26.1, pp. 616-619 (1985); H. Kume, et al., "A Flash-Erase EEPROM Cell With An Asymmetric Source And Drain Structure," IDEM, paper 25.8, pp. 560-563 (1987); G. Samachisa, et al., "A 128K Flash EEPROM Using Double Polysilicon Technology," ISSC, paper 7.4, pp. 76-77 (1987); F. Masouka, et al., "A New Flash E.sup.2 prom Cell Using Triple Polysilicon Technology," IDEM, paper 17.3, pp. 464-466 (1984).
Typically, a FEEPROM memory cell transistor is considered programmed when it is in the high threshold voltage state, i.e. when its floating gate is negatively charged with trapped injected electrons. FEEPROM memory cell is typically assumed to store a logic "0" when in the programmed state. Similar to UV-EPROM, FEEPROM is programmed by injecting hot electrons into the floating gate of the memory cell. A FEEPROM memory cell is considered erased when it is in the low threshold voltage state, i.e. when its floating gate is depleted from trapped injected electrons. FEEPROM memory cell typically is assumed to store a logic "1" when in the erased state. Erasure is normally achieved via electron tunneling from the floating gate to either an erase electrode as described in Masouka, or to one of the cell junctions as described in Mukherjee, Kume, and Samachisa.
Prior art FEEPROM memory cells are shown in FIGS 1a-1c and 2a-2c. Typically, the prior art FEEPROM memory cells are programmed by applying a voltage (V.sub.CG) on control gate 16, typically of about 12 V-14 V, and a voltage (V.sub.D) on drain 15, typically of about 7.5 V-10 V, while grounding source 14, (V.sub.S =0 V).
FIGS. 1a-1c show an example of a prior art single transistor memory cell 10 in terms of its topographical layout (FIG. 1a), schematic representation (FIG. 1b) and its cross-sectional view (FIG. 1c). When floating gate 18 is electrically neutral or slightly positively charged, memory cell 10 is in the `erased` state, and memory cell 10 has a low threshold voltage (Vte) typically of about 1.5 volts. When floating gate 18 is negatively charged, transistor 10 is programmed, and it has a high threshold voltage (Vtp), typically of about 6.5 volts.
Memory cell 10 is "programmed" by applying a high voltage of about 12 v-14 v to control gate 16 and a high voltage of about 8 v-10 v to drain 15, while grounding source 14. Good capacitive coupling between control gate 16 and floating gate 18 improves the vertical electric field formed between substrate 28 and floating gate 18 to improve the programming efficiency of memory cell 10. The floating gate voltage (V.sub.F) can be expressed by: ##EQU1## V.sub.f =Control gate voltage; V.sub.G =Control gate voltage;
V.sub.D =Drain voltage; PA1 Q.sub.F =Net charge stored on the floating gate; PA1 C.sub.FG =Floating gate to control gate capacitance; PA1 C.sub.FD =Floating gate to drain capacitance; PA1 C.sub.FS =Floating gate to source capacitance; and PA1 C.sub.FB =Floating gate to substrate capacitance.
The voltage coupled to the floating gate from the control gate (V.sub.F) is controlled by the following ratio, also referred to as the programming coupling ratio, ##EQU2## C.sub.TOT =Floating gate total capacitance.
Increasing the programming coupling ratio as expressed in equation (2) increases the efficiency of the floating gate to collect hot electrons and, thus, also increases the programming efficiency of the FEEPROM memory cell. The programming coupling ratio can be increased either by decreasing the floating gate to substrate capacitance (C.sub.FB) or by increasing the floating gate to control gate (C.sub.FG) capacitance. One way to increase this ratio without increasing the memory cell size is by increasing C.sub.FG through the use of special dielectrics of high dielectric constant between floating gate 18 and control gate 16 such as with an oxide nitride oxide (ONO) sandwich which has generally been used in more recent EPROM cells.
The programming efficiency can also be enhanced through enhancing the efficiency of hot electron generation. This can be achieved by having a higher electric field at drain injunction 11 where hot electrons are generated. Enhancement of hot electron generation is accomplished by using a shallower drain junction as well as using P.sup.+ type implant surrounding the drain junction.
Typically, memory cell 10 is "erased" by electron tunneling from floating gate 18 to source 14. This is accomplished by electrically grounding, relative to source 14, control gate 16 while a high voltage pulse of about 14 v-17 v is applied to source 14. Drain junction 15 is left to float to avoid punch through problems between source 14 and drain 15. Electron tunneling is appreciable at relatively high electric fields between 7 Mv/cm to 10 Mv/cm.
To achieve such high electric fields, the thickness of the first gate oxide between floating gate 18 and substrate 28 is reduced to prevent the need to use excessive voltages on chip. However, thinning gate oxide results in processing and reliability problems, and it also reduces the programming coupling ratio causing degradation in programming efficiency. Improving the programming coupling ratio of memory cell 10 necessitates increasing the cell size when the thickness of the first gate oxide is reduced: since the programming coupling ratio is decreased, the cell area must be increased to improve the programming coupling ratio. Improving the programming coupling ratio of memory cell 10 necessitates increasing the cell size. Thus, source 14 of memory cell 10 must withstand a high erase voltage (V.sub.e) without breakdown. Lowering the erase voltage by decreasing the thickness of first gate oxide 26 is also not a solution since the gated diode breakdown voltage is reduced for thinner gate oxides. To increase the gated diode breakdown of the source junction, a deeper doubly diffused N.sup.+ -N.sup.- junction is used.
The floating gate voltage during erase is given by: ##EQU3## V.sub.e =The erase voltage.
For more efficient erasure, V.sub.F, floating gate voltage should be minimized and, thus, the erase coupling ratio, expressed as ##EQU4## should be minimized.
Ideally, it is preferable to have FEEPROM arrays with one transistor per memory cell, a structure similar to UV-EPROMs. However, contrary to the self limiting nature of erasure by UV radiation, electrical erase is not self limiting. FEEPROM memory cell may become partially erased, where only part of the stored electron charge has been removed, or over-erased where the floating gate may become positively charged, depending on the applied erase voltage and applied erase time. An over-erased FEEPROM memory cell threshold voltage may result in a negative threshold voltage causing the over-erased FEEPROM cell to become a depletion transistor memory cell.
Prior art FEEPROM cell structures approached the over-erase problem by using a merged transistor memory cell structure with a single control gate covering the full length of the channel between the drain and source, and a floating gate only covering part of the channel length. Such merged transistor structure is equivalent to two transistors in series, a programmable transistor and an access transistor, but without a separation of the transistors by a physical junction. The programmable transistor controls the programming of the memory cell, while the access transistor limits the current and prevents an incorrect reading of the stored data if the programmable transistor is over-erased into depletion mode. In typical prior art merged transistor FEEPROMs, the part of the channel covered by the floating gate acts as the programmable transistor while the part of the channel covered only by the control gate acts as the access transistor. Such a structure avoids over-erase problems, while reducing the cell size, when compared to conventional merged transistor type EEPROMs.
Shown in FIGS. 2a-2c is a prior art merged transistor FEEPROM memory cell 20. Similar to the prior art EEPROM cells, merged transistor memory cell 20 operates in effect as two transistors in series, an access transistor and a programmable transistor. The access transistor is controlled via access portion (L.sub.a) 17 of control gate 16, while the programmable transistor is controlled via portion (LP) 19 of floating gate 18. The access transistor alleviates over-erase problems by preventing current flow through unselected memory cells of an array of memory cells. Merged transistor FEEPROM memory cell 20 not only provides two series transistors, but it is smaller in cell size than the typical two transistor per cell EEPROM, since memory cell 20 eliminates the physical junction normally separating the two series transistors.
When programmed, the effective threshold voltage of memory cell 20 equals the threshold voltage of the programmable transistor. Even if the programmable transistor is erased into depletion, the overall effective threshold voltage of memory cell 20 will remain positive, limited by the threshold voltage of the access transistor. Thus the effective overall threshold voltage is limited to the higher of either the programmable transistor or the access transistor. To program, floating gate 18 is charged with excess electrons which increases the threshold voltage of programmable transistor region 19 of memory cell 20. With floating gate 18 of memory cell 20 overlapping only drain junction 15, the electrical erase of memory cell 20 is also performed at drain junction 15. Effectively, both programming and erasing of memory cell 20 are thus performed at drain junction 15.
The programming conditions of memory cell 20 are similar to those of memory cell 10. However, programming for cell 20 is inherently less efficient since the lateral electric field is reduced due to the voltage drop across the access transistor. This voltage drop can be compensated by increasing the drain voltage during the programming mode of memory cell 20. However, increasing the drain voltage risks erasure of unselected memory cells of the same column in an array erase.
The erase conditions of memory cell 20 are similar to those of memory cell 10 with the exception that the erase pulse is to be applied to drain junction 15, while source junction 14 is floated.
For memory cell 20, both programming and erasure are performed at the drain junction, which imposes conflicting requirements on the drain junction. Shallow drain with P+ background implant is preferable for improved programming performance, while deeper drain junctions with preferably N- background implant is preferable for better erase performance. Optimizing the drain junction profile for these conflicting requirements typically compromises memory cell performance.
The conditions for the different operating modes of cells 10 and 20 are summarized as shown in Table 1.
TABLE 1 ______________________________________ FEEPROM Operating Modes PROGRAM ERASE READ ______________________________________ Cell 10 V.sub.CG .about.14V 0V .about.4.5V V.sub.D 7-9V float .about.1.75V V.sub.S 0V V.sub.e 0V Cell 20 V.sub.CG 14V 0V .about.4.5V V.sub.D 8-10V V.sub.e .about.1.75V V.sub.S 0V float 0V ______________________________________
Thus, the prior art FEEPROM memory cell structures can be generally classified into single transistor memory cell structure and merged transistor cell structure. In both types of prior art embodiments of FEEPROM memory cell structures, first polysilicon layer (poly1) 11 deposited over substrate 28 between drain 15 and source 14 forms floating gate 18 of memory cells 10 and 20, while second polysilicon layer (poly2) 12 deposited over floating gate 18 forms control gate 16.
Single transistor FEEPROM memory cell structures, such as those described in S. Mukherjee, et al., and Kume, et al., suffer from over-erase problems causing this type of FEEPROM memory cells to result in unreliable erase and programming performance. Single transistor FEEPROM memory cells exhibit over-erase problems at all junction profiles. Even at low erase currents, these cells may erase to voltages below their threshold values if erase time is sufficiently long. The threshold voltage of single transistor FEEPROM memory cell may even become negative changing the memory cell into a depletion device. In a full array erase, these changes in memory cell erase threshold value may result in an unreliable erase of the memory cells due to some memory cells becoming depletion devices. Single transistor FEEPROM memory cells therefore require a strict control of both the erase current and erase time to be exercised. However, even under such conditions, the array erase reliability cannot be guaranteed.
Prior art merged transistor FEEPROM memory cell structure with two polysilicon layer technology as described in Samachisa, et al., avoids the over-erase problem by using an integral select transistor in the part of the memory cell. This approach allows both programming and erasure to be accomplished at the drain junction of the merged transistor. However, this approach requires tight process control to optimize both the erase and programming requirements at the drain junction.
Another embodiment of a prior art merged transistor FEEPROM memory cell structure as described in Masouka, et al., incorporates a triple polysilicon layer technique, where a first polysilicon layer is used as an erase electrode, a second polysilicon layer is used as a floating gate, and a third polysilicon layer formed over the floating gate acts as the control gate of the merged transistor. This approach is disadvantageous since the floating gate is spaced away from the drain junction, requiring higher programming voltages, greater power consumption, and resulting in unreliable programming operation. This type of structure also requires excessively high voltages for both programming and erasure which limits the practicality and manufacturability of this structure.
There is therefore a need for improved FEEPROM memory cells which provides an improvement to memory cell programming and erasure performance, without increasing FEEPROM programming voltage or cell size.